The present invention relates to a semiconductor device and a method of fabricating the same and, more particularly, to a memory cell transistor structure suitable for a logic/DRAM hybrid device and a method of fabricating the same.
Recently, to realize high-speed, large-amount data transfer with respect to memories, a technique capable of forming both a logic circuit and a DRAM on one chip is being required. In a logic circuit device, a technique which reduces the resistance by adhering metal silicide to a gate electrode and source and drain diffusion layers of a MOS transistor is conventionally used to improve the circuit performance. Accordingly, it is desirable to apply a similar resistance reducing technique to a DRAM cell in a logic/DRAM hybrid device.
In a DRAM cell, however, it is presumably better not to adhere metal silicide to source and drain regions in order to suppress a leakage current in a junction connecting to a memory capacitor and thereby improve the charge holding characteristic (e.g., "Trade-offs in the Integration of High Performance Devices with Trench Capacitor DRAM", S. Crowder et al., pp. 45-48, IEDM971). One reason is that when a metal silicide film is formed on the surfaces of source and drain regions, this metal silicide may penetrate through diffusion layers to cause junction leakage. Also, forming a metal silicide film requires the formation of a heavily doped impurity diffusion layer having a dose of about 1E15/cm.sup.2 or more in source and drain regions. When such a heavily doped impurity diffusion layer is formed, junction leakage increases due to this heavily doped impurity diffusion layer.
In the fabrication of a logic/DRAM hybrid device, it is important to reduce the number of fabrication steps. Therefore, it is required to develop a logic/DRAM hybrid device fabrication technique which simplifies the fabrication process, reduces the resistance of source and drain diffusion layers and a gate electrode, and retains the charge holding characteristic of a memory capacitor.
If regions are separated in one chip such that metal silicide is adhered in a logic circuit and is not adhered in a DRAM cell array, it is necessary to add a mask step and an accompanying processing step. This increases the number of fabrication steps.